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CY62126DV30 MoBL
1-Mbit (64K x 16) Static RAM
Features
* Very high speed: 45 ns * Wide voltage range: 2.2V to 3.6V * Pin compatible with CY62126BV * Ultra-low active power -- Typical active current: 0.85 mA @ f = 1 MHz -- Typical active current: 5 mA @ f = fMAX * Ultra-low standby power * Easy memory expansion with CE and OE features * Automatic power-down when deselected * Packages offered in a 48-ball FBGA and a 44-lead TSOP Type II * Also available in Lead-free packages also has an automatic power-down feature that significantly reduces power consumption by 90% when addresses are not toggling. The device can be put into standby mode reducing power consumption by more than 99% when deselected (CE HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH) or during a write operation (CE LOW and WE LOW). Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A15). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes.
Functional Description[1]
The CY62126DV30 is a high-performance CMOS static RAM organized as 64K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery LifeTM (MoBL(R)) in portable applications such as cellular telephones. The device
Logic Block Diagram
DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
ROW DECODER
64K x 16 RAM Array 2048 x 512
SENSE AMPS
I/O0-I/O7 I/O8-I/O15
COLUMN DECODER BHE WE CE OE BLE
A12
A11
A13
Note: 1. For best-practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com.
Cypress Semiconductor Corporation Document #: 38-05230 Rev. *E
*
3901 North First Street
A14 A15
*
San Jose, CA 95134 * 408-943-2600 Revised February 2, 2005
CY62126DV30 MoBL
Pin Configurations[2, 3]
FBGA (Top View) 4 5 3 A0 A3 A5 NC A1 A4 A6 A7 NC A15 A13 A10 A2 CE I/O1 I/O3 I/O4 I/O5 WE A11 TSOP II (Forward) Top View A B C D E F G H A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
1 BLE I/O8 I/O9 VSS VCC I/O14 I/O15 NC
2 OE
6 NC I/O0 I/O2 VCC VSS I/O6 I/O7 NC
BHE I/O10 I/O11
I/O12 DNU I/O13 NC A8 A14 A12 A9
A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC
Product Portfolio
Power Dissipation Operating, ICC (mA) VCC Range (V) Product CY62126DV30L CY62126DV30LL CY62126DV30L CY62126DV30LL CY62126DV30L CY62126DV30LL 2.2 3.0 3.6 2.2 3.0 3.6 Min. 2.2 Typ. 3.0 Max. 3.6 Speed (ns) 45 45 55 55 70 70 f = 1 MHz Typ.[4] 0.85 0.85 0.85 0.85 0.85 0.85 Max. 1.5 1.5 1.5 1.5 1.5 1.5 f = fMAX Typ.[4] 6.5 6.5 5 5 5 5 Max. 13 13 10 10 10 10 Standby, ISB2 (A) Typ.[4] 1.5 1.5 1.5 1.5 1.5 1.5 Max. 5 4 5 4 5 4
Notes: 2. NC pins are not connected to the die. 3. E3 (DNU) can be left as NC or VSS to ensure proper operation. (Expansion Pins on FBGA Package: E4 - 2M, D3 - 4M, H1 - 8M, G2 - 16M, H6 - 32M). 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25C.
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CY62126DV30 MoBL
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage to Ground Potential ........................................................... -0.3V to 3.9V DC Voltage Applied to Outputs in High-Z State[5.] ...................................-0.3V to VCC + 0.3V DC Input Voltage[5] ................................ -0.3V to VCC + 0.3V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current .................................................... > 200 mA
Operating Range
Range Industrial Ambient Temperature (TA) -40C to +85C VCC[6.] 2.2V to 3.6V
DC Electrical Characteristics (Over the Operating Range)
CY62126DV30-45 Parameter Description VOH VOL VIH Test Conditions Min. Typ.[4] Output HIGH 2.2 < VCC < 2.7 IOH = -0.1 mA 2.0 Voltage 2.7 < VCC < 3.6 IOH = -1.0 mA 2.4 Output LOW 2.2 < VCC < 2.7 IOL = 0.1 mA Voltage 2.7 < VCC < 3.6 IOL = 2.1 mA Input HIGH Voltage 2.2 < VCC < 2.7 2.7 < VCC < 3.6 VIL Input LOW Voltage 2.2 < VCC < 2.7 2.7 < VCC < 3.6 IIX Input Leakage Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-down Current - CMOS Inputs Automatic CE Power-down Current- CMOS Inputs GND < VI < VCC 1.8 2.2 -0.3 -0.3 -1 0.4 0.4 VCC + 0.3 VCC + 0.3 0.6 0.8 +1 1.8 2.2 -0.3 -0.3 -1 CY62126DV30-55 CY62126DV30-70 2.0 2.4 0.4 0.4 VCC 1.8 + 0.3 VCC 2.2 + 0.3 0.6 0.8 +1 -0. 3 -0. 3 -1 2.0 2.4 0.4 0.4 VCC + 0.3 VCC + 0.3 0.6 0.8 +1 A V V V V Max. Min. Typ.[4] Max. Min Typ.[4] Max. Unit
IOZ
GND < VO < VCC, Output Disabled f = fMAX = 1/tRC f = 1 MHz VCC = 3.6V, IOUT = 0 mA, CMOS level
-1
+1
-1
+1
-1
+1
A
ICC
6.5 0.85 1.5 1.5
13 1.5 5 4
5 0.85 1.5 1.5
10 1.5 5 4
5 0.85 1.5 1.5
10 1.5 5 4
mA
ISB1
CE > VCC - 0.2V, L VIN > VCC - 0.2V, VIN < 0.2V, LL f = fMAX (Address and Data Only), f = 0 (OE, WE, BHE and BLE) CE > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, f = 0, VCC = 3.6V L LL
A
ISB2
1.5 1.5
5 4
1.5 1.5
5 4
1.5 1.5
5 4
A
Notes: 5. VIL(min.) = -2.0V for pulse durations less than 20 ns., VIH(max.) = VCC + 0.75V for pulse durations less than 20 ns. 6. Full device operation requires linear ramp of VCC from 0V to VCC(min) & VCC must be stable at VCC(min) for 500 s.
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CY62126DV30 MoBL
Capacitance[7]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz VCC = VCC(typ) Max. 8 8 Unit pF pF
Thermal Resistance
Parameter JA JC Description Thermal Resistance (Junction to Ambient)[7] Thermal Resistance (Junction to Case)[7] Test Conditions Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board TSOP 55 12 FBGA 76 11 Unit C/W C/W
AC Test Loads and Waveforms[8]
R1 VCC OUTPUT 50 pF INCLUDING JIG AND SCOPE Equivalent to: OUTPUT THEVENIN EQUIVALENT RTH VTH R2
ALL INPUT PULSES VCC Typ GND Rise TIme: 1 V/ns 10% 90% 90% 10% Fall Time: 1 V/ns
Parameters R1 R2 RTH VTH
2.5V 16600 15400 8000 1.2
3.0V 1103 1554 645 1.75
Unit Ohms Ohms Ohms Volts
Data Retention Characteristics
Parameter VDR ICCDR tCDR tR[9]
[7]
Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time
Conditions VCC=1.5V, CE > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V L LL
Min. 1.5
Typ.[4]
Max. 4 3
Unit V A ns s
0 100
Notes: 7. Tested initially and after any design or proces changes that may affect these parameters. 8. Test condition for the 45 ns part is a load capacitance of 30 pF 9. Full device operation requires linear VCC ramp from VDR to VCC(min.) >100 s.
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CY62126DV30 MoBL
Data Retention Waveform
DATA RETENTION MODE VDR > 1.5 V
VCC CE
VCC(min)
tCDR
VCC(min)
tR
Switching Characteristics (Over the Operating Range)[10]
CY62126DV30-45[8] Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z[11] OE HIGH to High CE LOW to Low CE HIGH to High Z[11, 12] 10 20 0 45 25 5 15 45 40 40 0 0 35 40 25 0 15 10 10 55 40 40 0 0 40 40 25 0 20 5 5 20 70 60 60 0 0 50 60 30 0 25 0 55 25 5 25 Z[11, 12] Z[11] 5 15 10 20 0 70 35 10 45 25 5 20 10 25 45 45 10 55 25 5 25 55 55 10 70 35 70 70 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. CY62126DV30-55 Min. Max. CY62126DV30-70 Min. Max. Unit
CE LOW to Power-up CE HIGH to Power-down BLE/BHE LOW to Data Valid BLE/BHE LOW to Low Cycle[13] Write Cycle Time CE LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width BLE/BHE LOW to Write End Data Set-up to Write End Data Hold from Write End WE LOW to High Z
[11, 12]
Z[11]
BLE/BHE HIGH to High-Z[11, 12]
WE HIGH to Low Z[11]
Notes: 10. Test conditions assume signal transition time of 1V/ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL. 11. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE. 12. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state. 13. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
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CY62126DV30 MoBL
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[14, 15]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Read Cycle No. 2 (OE Controlled)[15, 16]
ADDRESS
CE tACE OE
tDOE
tRC tPD tHZCE
tHZOE
BHE/BLE
ttLZOE LZOE
tHZBE tLZBE DATA OUT
tDBE
DATA VALID HIGH IMPEDANCE
HIGH IMPEDANCE tLZCE
VCC SUPPLY CURRENT
tPU 50% 50%
ICC ISB
Notes: 14. Device is continuously selected. OE, CE = VIL, BHE, BLE = VIL. 15. WE is HIGH for Read cycle. 16. Address valid prior to or coincident with CE, BHE, BLE transition LOW.
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CY62126DV30 MoBL
Switching Waveforms(continued)
Write Cycle No. 1 (WE Controlled[12, 13, 16, 17, 18]
tWC ADDRESS tSCE CE tAW WE tSA tPWE tHA
BHE/BLE
tBW
OE tSD DATA I/O NOTE 19 tHZOE DATAIN VALID tHD
Write Cycle No. 2 (CE Controlled)[12, 13, 16, 17, 18]
tWC ADDRESS tSCE CE
tSA
tAW tPWE
tHA
WE
BHE/BLE
tBW
OE tSD DATA I/O NOTE 19 tHZOE DATAIN VALID tHD
Notes: 17. Data I/O is high-impedance if OE = VIH. 18. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 19. During the DON'T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
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CY62126DV30 MoBL
Switching Waveforms(continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[17, 18]
tWC ADDRESS tSCE CE tBW tAW tSA WE tSD DATAI/O NOTE 19 tHZWE DATAIN VALID tLZWE tHD tPWE tHA
BHE/BLE
Write Cycle No. 4 (BHE-/BLE-controlled, OE LOW)[17, 18]
tWC ADDRESS
CE tSCE
tAW BHE/BLE tSA WE tPWE tSD DATA I/O tHD tBW tHA
NOTE 19
DATAIN VALID
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CY62126DV30 MoBL
Truth Table
CE H L L L L L L L L L L WE X X H H H H H H L L L OE X X L L L H H H X X X BHE X H L H L L H L L H L BLE X H L L H L L H L L H Inputs/Outputs High Z High Z Data Out (I/OO-I/O15) Data Out (I/OO-I/O7); I/O8-I/O15 in High Z Data Out (I/O8-I/O15); I/O0-I/O7 in High Z High Z High Z High Z Data In (I/OO-I/O15) Data In (I/OO-I/O7); I/O8-I/O15 in High Z Data In (I/O8-I/O15); I/O0-I/O7 in High Z Mode Deselect/Power-Down Output Disabled Read Read Read Output Disabled Output Disabled Output Disabled Write Write Write Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 45 Ordering Code CY62126DV30LL-45BVI CY62126DV30LL-45BVXI CY62126DV30LL-45ZSXI 55 CY62126DV30L-55BVI CY62126DV30LL-55BVI CY62126DV30L-55ZSI CY62126DV30LL-55ZSI CY62126DV30LL-55ZSXI 70 CY62126DV30L-70BVI CY62126DV30LL-70BVI CY62126DV30L-70ZSI CY62126DV30LL-70ZSI CY62126DV30LL-70ZSXI BV48A BV48A ZS44 ZS44 ZS44 BV48A BV48A ZS44 ZS44 Package Name BV48A Package Type 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) (Pb-free) 44-Lead TSOP Type II (Pb-free) 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) 44-Lead TSOP Type II 44-Lead TSOP Type II 44-Lead TSOP Type II (Pb-Free) 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) 44-Lead TSOP Type II 44-Lead TSOP Type II 44-Lead TSOP Type II (Pb-Free) Industrial Industrial Operating Range Industrial
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CY62126DV30 MoBL
Package Diagrams
48-Lead VFBGA (6 x 8 x 1 mm) BV48A
51-85150-*B
44-pin TSOP II ZS44
51-85087-*A
MoBL is a registered trademark, and MoBL2 and More Battery Life are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY62126DV30 MoBL
Document History Page
Document Title: CY62126DV30 MoBL 1- Mbit (64K x 16) Static RAM Document Number: 38-05230 REV. ** *A ECN NO. Issue Date 117689 127313 08/27/02 06/13/03 Orig. of Change JUI MPR Description of Change New Data Sheet Changed From Advanced Status to Preliminary. Changed ISB2 to 5 A (L), 4 A (LL) Changed ICCDR to 4 A (L), 3 A (LL) Changed CIN from 6 pF to 8 pF Changed from Preliminary to Final Add 70-ns speed, updated ordering information Changed ICC 1 MHz typ from 0.5 mA to 0.85 mA Fixed typo: Changed tDBE from 70 ns to 35 ns Added 45-ns Speed Bin in AC, DC and Ordering Information tables Added Footnote #8 on page #4 Added Pb-Free package ordering information on page # 9 Changed 44-pin TSOP-II package name from Z44 to ZS44
*B *C *D *E
128340 129002 238050 316039
07/22/03 08/29/03 See ECN See ECN
JUI CDY AJU PCI
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